1. Field of the Invention
The present invention relates to the art of electronic packaging, and more specifically to components useful for mounting and/or testing semiconductor chips and related electronic components. The present invention also relates to semiconductor chip assemblies and electronic devices incorporating such components.
2. Description of the Related Art
Modern electronic devices utilize semiconductor components, commonly referred to as xe2x80x9cintegrated circuitsxe2x80x9d which incorporate numerous electronic elements. These chips are mounted on substrates that physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be part of a discrete chip package, such as a single chip module or a multi-chip module, or may be a circuit board. The chip module or circuit board is typically incorporated into a large circuit. An interconnection between the chip and the chip module is commonly referred to as a xe2x80x9cfirst levelxe2x80x9d assembly or chip interconnection. An interconnection between the chip module and a printed circuit board or card is commonly referred to as a xe2x80x9csecond levelxe2x80x9d interconnection. In xe2x80x9cchip on boardxe2x80x9d packaging, the chip is mounted directly on the printed circuit board. This type of interconnection has been referred to as a xe2x80x9c1xc2xd levelxe2x80x9d interconnection.
One relatively common packaging scheme is called a xe2x80x9chybrid circuitxe2x80x9d. A hybrid circuit typically contains a semiconductor chip that has been mounted and electrically interconnected to a circuit that has been formed on a thin layer of a rigid ceramic material. The method used to electrically interconnected the chip to the circuit is generally any of the methods that are known for use in first level bonding, such as wire bonding, tab bonding and flip chip bonding. In some cases it is desirable to mount and electrically interconnect the hybrid circuit to a printed circuit board. Solder is typically used to form the interconnection. It is difficult, however, to rework a hybrid circuit that has been soldered to a printed circuit board. In order to rework the assembly, the hybrid circuit must be removed from the printed circuit board. When the hybrid circuit is separated from the printed circuit board, part of the solder mass is removed from the contacts on the hybrid circuit. Non-uniform partial solder masses remain on the hybrid circuit contacts, the printed circuit board or both. When the hybrid circuit is resoldered to the printed circuit board, the non-uniform partial solder masses can cause short circuits and alignment problems.
Another problem associated with the assembly process is testing. In a typical assembly process, each hybrid circuit is tested before it is soldered to a printed circuit board. Testing involves clamping the hybrid circuit to a socket to engage the solder balls of the hybrid circuit with the test contacts of the test assembly. When the solder balls are engaged with the test contacts, the solder tends to creep and to deform, especially if the hybrid circuit is equipped with high-lead solder. The testing process, like the rework process, can lead to short circuit and alignment problems. To overcome these problems, it is desirable to use solid core solder balls to interconnect the ceramic substrate to a printed circuit board.
In U.S. Pat. No. 3,303,393, which issued on Feb. 7, 1967, Hymes et al. disclose a semiconductor chip assembly with flip-chip connections, which incorporates copper core solder balls. One solid core solder ball is provided between each contact on the chip and each contact pad on the substrate. Although these connections work well for small devices, with larger devices, the rigid connections provided by the solid core solder balls tend to crack at the soldered junctions between the balls and the opposing surfaces. Warpage or distortion of the chip or substrate, furthermore, make it difficult to engage all of the solid core solder balls between the chip and substrate simultaneously, or to engage all of the solid core solder balls between the chip and a test fixture. Although it is desirable to use solid core solder balls to interconnect a hybrid circuit to a printed circuit board, such an interconnection would be subject to similar problems.
The electrical power that is dissipated when a microelectronic device is in operation tends to heat up that device. When the device is no longer in operation, it tends to cool down. Over a period of time, the device tends to undergo a number of heating up and cooling down cycles as the device is repeatedly turned on and off. These cycles, which cause an associated expansion and contraction of the device, are commonly referred to as xe2x80x9cthermal cyclingxe2x80x9d.
A device in which a hybrid circuit is bonded to a printed circuit board using solid core solder balls would be subject to substantial strain, caused by thermal cycling, during operation of the device. Electrical power dissipated within the hybrid circuit during operation would tend to heat up the hybrid circuit and, to a lesser extent, the printed circuit board. The temperature of the hybrid circuit, therefore, and, to a lesser extent, the printed circuit board would rise each time the device is turned on and fall each time the device is turned off. Since the hybrid circuit and the printed circuit board are normally constructed from different materials having different coefficients of thermal expansion, the hybrid circuit and printed circuit board would normally expand and contract by different amounts. This is commonly referred to as a xe2x80x9cthermal mismatchxe2x80x9d. The thermal mismatch causes the electrical contacts on the hybrid circuit to move relative to the electrical contact pads on the printed circuit board as the temperature of the hybrid circuit and printed circuit board change. The relative movement would deform the electrical interconnections between the hybrid circuit and the printed circuit board and place them under mechanical stress. Since these stresses would be applied repeatedly with repeated operation of the device, they would cause breakage of the electrical interconnections. Thermal cycling stresses may occur even where the hybrid circuit and printed circuit board are formed from like materials having similar coefficients of thermal expansion. This is because the temperature of the hybrid circuit may increase more rapidly than the temperature of the printed circuit board when power is first applied to the hybrid circuit. Unfortunately, solid core solder balls are neither flexible nor strong enough to withstand the strain generated by differential rates of thermal expansion.
Commonly assigned U.S. Pat. Nos. 5,148,265; 5,148,266; 5,518,964; 5,659,952; 5,929,517; 5,679,977; 5,685,885; 5,848,467; 5,852,326; 5,950,304; 6,133,627; 5,801,441; 6,104,087; 5,798,286; 5,830,782; 5,959,354; 5,913,109; 6,080,603; and 5,688,716; and U.S. patent application Ser. No. 09/271,688, filed on Mar. 18, 1999, the specifications of which are incorporated by reference herein, provide substantial solutions to the problems of thermal stresses and component testing. Nonetheless, still further improvement is desirable.
One aspect of the present invention provides a flexible chip carrier. The flexible chip carrier of this aspect of the present invention includes a rigid interposer having first and second surfaces. The rigid interposer is preferably adapted to mount and electrically connect a semiconductor chip onto the first surface of the rigid interposer. An interconnection between the rigid interposer and a semiconductor chip is a xe2x80x9cfirst levelxe2x80x9d interconnection. The rigid interposer may be adapted to interconnect a semiconductor chip using any of the known methods of creating xe2x80x9cfirst levelxe2x80x9d interconnections. Some conventional xe2x80x9cfirst levelxe2x80x9d interconnection methods include wire bonding, tape-automated bonding and flip-chip bonding. The second surface contains a plurality of contacts disposed in a pattern. The area encompassed by the contacts is defined as a xe2x80x9ccontact pattern areaxe2x80x9d. The rigid interposer is preferably a thin, sheet-like layer material. The rigid interposer may be composed of any rigid dielectric material. Preferred rigid dielectric materials include ceramic materials, such as alumina, beryllia, silicon carbide, aluminum nitride, forsterite, mullite, and glass-ceramics; composite materials, such as polyester/fiberglass, polyimide/fiberglass, and epoxy/fiberglass; and silicon. More preferred rigid dielectric materials are the ceramic materials listed above. The preferred ceramic material is alumina. On preferred embodiments, the rigid interposer contains an electrical circuit. Although the coefficient of thermal expansion, hereinafter xe2x80x9cCTExe2x80x9d, of the rigid interposer is generally greater than the CTE of a semiconductor chip and generally less than the CTE of an epoxy-polyimide printed circuit board, the CTE of the rigid interposer may be roughly equal to the CTE of the semiconductor chip. This is because other sub-components of the present invention, specifically the flexible interposer and/or the optional compliant layer can compensation for the CTE mismatch between chip and the rigid interposer and the CTE mismatch between the rigid interposer and the flexible interposer.
The flexible chip carrier also includes a flexible interposer that overlies the second surface of the rigid interposer. The flexible interposer has a top surface that faces toward the second surface of the rigid interposer, and a bottom surface that does not. The flexible interposer preferably is a thin, flexible sheet of a polymeric material such as polyimide, a fluoropolymer, a thermoplastic polymer or an elastomer. In preferred embodiments, the flexible interposer contains an electrical circuit. The flexible interposer may have one or more apertures, extending from the top surface of the flexible interposer to the bottom surface.
A plurality of electrically conductive terminals is disposed on the flexible interposer in a pattern on at least one surface selected from the group consisting of the top surface and the bottom surface. In preferred embodiments, either all of the terminals disposed on the top surface or all of the terminals are disposed on the bottom surface of the flexible interposer. At least some of the terminals, and preferably most or all of the terminals, are disposed within the area of the flexible interposer overlying the contact pattern area on the rigid interposer. Generally, each terminal is associated with one contact on the rigid interposer.
The flexible chip carrier also includes a plurality of electrically conductive leads connecting at least some of the contacts on the rigid interposer with at least some of the terminals on the flexible interposer. Each lead has a contact end connected to the associated contact on the rigid interposer and a terminal end connected to the associated terminal on the flexible interposer. The leads and the flexible interposer are constructed and arranged so that the contacts ends of the leads are moveable relative to the terminals at least to the extent required to compensate for differential thermal expansion between the components. The interconnection between the contacts on the rigid interposer and the terminals on the flexible interposer is a second xe2x80x9cfirst levelxe2x80x9d interconnection. The leads are preferably flexible so that the terminals are moveable with respect to the contacts to accommodate movement caused by differential thermal expansion.
The flexible interposer is flexible to facilitate movement of the contact ends of the leads relative to the terminals and thus to contribute to the ability of the chip carrier to withstand thermal cycling. Each flexible lead may extend through an aperture in the flexible interposer. The flexible leads may be formed integrally with the terminals on the flexible interposer, or else may be separately formed fine wires. Preferably, the leads are curved to provide increased flexibility. The leads may be generally S-shaped. Each lead may be formed from a ribbon of conductive materials having oppositely-directed major surfaces, the ribbon being curved in directions normal to its major surfaces to form a curved configuration of the lead In a preferred embodiment, the lead is S-shaped.
Some preferred arrangements of leads connecting the contacts to the terminals include a xe2x80x9cfan-inxe2x80x9d, xe2x80x9cfan-outxe2x80x9d, xe2x80x9cfan-in/fan-outxe2x80x9d, and area array. In a xe2x80x9cfan-inxe2x80x9d arrangement, the contacts on the rigid interposer are typically disposed on the periphery of the rigid interposer. The terminals are generally disposed inside the region that overlies the region bounded by the contacts on the rigid interposer. The leads connecting the terminals to the associated contacts fan inwardly. In a xe2x80x9cfan-outxe2x80x9d arrangement, the contacts on the rigid interposer are again generally disposed on the periphery of the rigid interposer, and the terminals on the flexible interposer are generally disposed in a region that is outside the region that overlies the region bounded by the contacts. The leads connecting the terminals to the associated contacts fan outwardly. In a xe2x80x9cfan-in/fan-outxe2x80x9d arrangement, some terminals on the flexible interposer are disposed inside the region bounded by the contacts and some are disposed outside the region. Some leads, therefore, fan-in and some fan-out. The rigid interposer contacts typically are disposed in single rows and columns on the second surface and the leads are interdigitated. By the term xe2x80x9cinterdigitatedxe2x80x9d, it is meant that that fan-in and fan-out leads are interspersed with one another. The preferred interdigitated fan-in/fan-out arrangement is where each lead that is adjacent to a fan-in lead is a fan-out lead and each lead that is adjacent to a fan-out lead is a fan-in lead. In an xe2x80x9carea arrayxe2x80x9d arrangement, the contacts on the rigid interposer may be disposed on the periphery of the rigid interposer or may be disposed in a so called area array, i.e., a grid like pattern covering all or a substantial portion of the bottom surface of the rigid interposer. For the leads to be in an area array arrangement, however, the terminals on the flexible interposer must be disposed in area array.
The flexible chip carrier further includes a plurality of joining units. In certain preferred embodiments, each joining unit includes a solid core which is preferably spherical. Each joining unit is disposed on the bottom surface of the flexible interposer, is electrically interconnected to one terminal, and extends downwardly from such terminal. If any terminals are disposed on the bottom surface of the flexible interposer, one of said joining units is preferably disposed directly on each of such terminals. The solid cores are preferably electrically conductive. Preferably, the solid cores are made from copper or nickel.
The flexible chip carrier also includes a unit bonding material. The unit bonding material extends between the terminal and the solid core. Preferably, the unit bonding material is standard lead/tin solder and is provided as a part of the joining unit, as a coating extending over the solid core. The unit bonding material may be used to bond the flexible chip carrier to a printed circuit board or another support substrate.
The flexible chip carrier may also include a compliant layer covering the flexible leads in whole or in part. The compliant layer comprises a dielectric material having a low modulus of elasticity, such as an elastomeric material. Preferred elastomeric materials include silicones, flexiblized epoxies, and thermoplastics. Silicone elastomers are particularly preferred. The dielectric material may be provided in the form of a layer, with holes in the layer aligned with the terminals on the flexible interposer. In preferred embodiments, the compliant layer is formed in at least a two-step process. The first step involves dispensing a controlled amount of a thixotropic or non-slumping silicone elastomer on a portion, but not all, of the bottom surface of the rigid interposer and/or a portion, but not all, of the first surface of the flexible interposer, to create a compliant spacer. The compliant spacer controls the separation between the rigid interposer and the flexible interposer. The second step involves dispensing a second silicone elastomer over the thixotropic or non-slumping silicone elastomer. Compliant spacers and their use in microelectronic assemblies is more fully described in commonly assigned, U.S. Pat. No. 5,659,952, the specification of which is hereby incorporated by reference.
One aspect of the present invention provides a semiconductor chip assembly. The semiconductor chip assembly of the present invention includes the flexible chip carrier described above and at least one semiconductor chip that has been connected to the first surface of the rigid interposer of the flexible chip carrier. The semiconductor chip assembly of the present invention may contain a plurality of semiconductor chips.
If the semiconductor chip assembly contains a plurality of chips, each chip is mounted on and electrically interconnected to the rigid interposer of the flexible chip carrier. Such assemblies may be referred to as multichip modules. Such a multichip module may, for example, comprise a monolithic microwave integrated circuit and a high frequency digital integrated circuit on one rigid interposer that is part of a flexible chip carrier. If both of these high frequency elements are on one rigid interposer, the high frequency elements of the circuit can be isolated from the lower frequency elements. In another embodiment, an integrated circuit in the form of a central processing unit, sometimes referred to as a xe2x80x9ccpuxe2x80x9d, and one or more memory chips may be mounted on a rigid interposer of the present flexible chip carrier to form a semiconductor chip assembly of the present invention. Such an assembly would also be a multichip module.
Preferred methods of connecting the one or more semiconductor chips to the flexible chip carrier include wirebonding, flip chip bonding and tab bonding, with wire bonding and flip chip bonding being more preferred. If the semiconductor chip is to be wire bonded, the rigid interposer should have as plurality of electrically conductive pads disposed in a ring-like pattern. The chip is secured to the first surface of the rigid interposer at the center of the ring-like pattern, so that the contact pads on the rigid interposer surround the chip. The chip is mounted on the first surface of the rigid interposer. The chip is mounted on the rigid interposer in a face-up disposition, with the back surface of the chip confronting the first surface of the rigid interposer, and with the front surface of the chip facing upwardly, away from the rigid interposer so that the electrical contacts on the front surface of the chip are exposed. Fine wires are connected between the electrical contacts on the front surface of the chip and the contact pads on the first surface of the rigid interposer. These wires extend outwardly from the chip to the surrounding contact pads on the first surface of the rigid interposer.
If the semiconductor chip is to be connected to the rigid interposer using flip chip technology, the electrical contacts on the front surface of the chip are provided with bumps of solder. The first surface of the rigid interposer should include a plurality of contact pads arranged in an array corresponding to the array of electrical contacts on the chip. The chip, with the solder bumps, is inverted so that its front surface faces towards the first surface of the rigid interposer, with each electrical contact and solder bump on the chip being positioned on the appropriate contact pad on the first surface of the rigid interposer. The assembly is then heated so as to liquefy the solder and, upon resolidification of the solder, bond each contact on the chip to the confronting contact pad on the first surface of the rigid interposer.
The semiconductor chip assembly of the present invention has at least two xe2x80x9cfirst levelxe2x80x9d interconnections in the flexible chip carrier. The first xe2x80x9cfirst levelxe2x80x9d interconnection is the interconnection between the semiconductor chip and the rigid interposer and second xe2x80x9cfirst levelxe2x80x9d interconnection is the interconnection between the rigid interposer and the flexible interposer.
Another aspect of the present invention provides a test assembly for semiconductor chips. Current semiconductor chip manufacturing techniques do not result in 100% yields, some chips, therefore, will be defective. Often, the defect can not be detected until the chip is operated under power in a test fixture or in an actual assembly. A single bad chip can make a larger assembly, which may include other chips or other valuable components, worthless, or can require painstaking procedures to extricate the bad chip from the assembly. The chips and the mounting components used in a semiconductor chip assembly should, therefore, permit testing of the chips and replacement of the chips before the chips are fused to a substrate.
Semiconductor chips can be tested in the test assembly of the present invention. The test assembly of this aspect of the present invention includes the flexible chip carrier as described above. The test assembly further includes a sheet socket assembly or connector. Preferred sheet socket assemblies and connectors are those described in commonly assigned U.S. Pat. No. 5,615,824; U.S. Pat. No. 5,632,631; U.S. Pat. No. 5,802,699; and U.S. Pat. No. 6,086,386, the specifications of which are incorporated by reference herein.
In preferred embodiments, the sheet socket component or connector includes a planar or sheet like dielectric body having first and second major surfaces and also having a plurality of holes open to the first major surface. The second major surface faces toward the first surface of the rigid interposer of the flexible chip carrier. The holes are disposed in an array corresponding to an array of bumped leads on a semiconductor chip or microelectronic device which is to be tested. The sheet socket assembly further includes an array of resilient contacts secured to the first major surface of the dielectric body in registration with the holes so that each such resilient contact extends over one hole. Each resilient contact is adapted such that it can resiliently engage a bumped lead that has been inserted into the associated hole. The sheet socket assembly also includes a plurality of socket terminals electrically connected to these resilient contacts. Typically, the socket terminals are disposed on the second major surface of the dielectric body in an array corresponding to the array of contact pads on the first surface of the rigid interposer. The socket terminals are electrically connected to the associated resilient contacts. Preferably, each socket terminal is electrically connected to an associated resilient contact by an electrically conductive via, such as a blind via or a through hole via. The sheet socket assembly is mounted and electrically interconnected to the flexible chip carrier by bonding the socket terminals to the associated contact pad on the rigid interposer.
Another aspect of the present invention provides a semiconductor chip assembly comprising the test assembly described above and a semiconductor chip having solder bumps which have engaged and are in physical and electrical contact with the resilient contacts of the test assembly. In preferred embodiments of the semiconductor chip assembly of this aspect of present invention, the semiconductor chip is soldered to the test assembly.
If the semiconductor chip assembly of this aspect of the invention contains more than one chip, the assembly can be described as a multichip module assembly. Each chip of the multichip module can be individually plugged into the test socket assembly of the present invention and the system can be tested. If the system works properly, each of the chips can be soldered in permanently. In the alternative, a module containing at least two chips can be plugged into the test socket assembly and tested. If the system works properly, each of the chips can be soldered in permanently.
The semiconductor chip assembly of the present invention may be incorporated into a larger assembly to form an electronic device. Another aspect of the present invention, therefore, provides an electronic device. The electronic device includes the semiconductor chip assembly described above and a support substrate having pads. The pads are electrically conductive contact pads and are preferably disposed in a pattern corresponding to the pattern of solid core joining units, wherein each pad is associated with a solid core joining unit. The semiconductor chip assembly is positioned on the support substrate such that the bottom surface of the flexible interposer faces toward the support substrate and, preferably, such that the solid core joining units on the bottom surface of the flexible interposer are aligned with the pads on the support substrate. Generally, each solid core joining unit is physically and electrically interconnected to an associated pad on the support substrate.
The flexible chip carrier of the present invention may be incorporated into a larger assembly to form an electronic component. Another aspect of the present invention, therefore, provides an electronic component. The electronic component of the present aspect of the invention includes the flexible chip carrier described above and a support substrate having pads. The pads are electrically conductive contacts pads and are preferably disposed in a pattern corresponding to the pattern of solid core joining units, wherein each pad is associated with a solid core joining unit. The flexible chip carrier is positioned on the support substrate such that the bottom surface of the flexible interposer faces toward the support substrate and, preferably, such that the solid core joining units on the bottom surface of the flexible interposer are aligned with the pads on the support substrate. Generally, each solid core joining unit is physically and electrically interconnected to an associated pad on the support substrate. A semiconductor chip may be bonded to the electronic component to form an electronic device. Preferred bonding methods include wire bonding, flip chip bonding and tab bonding with wire bonding and flip chip bonding being particularly preferred.
Another aspect of the present invention provides a flexible chip carrier or connection component that includes a first, or rigid, interposer, a second, or flexible, interposer, a plurality of conductive structures and a plurality of planar leads. The first interposer has first and second surfaces that are oppositely facing, and the second interposer has top and bottom surfaces that are oppositely facing. The second surface of the first interposer is disposed over the top surface of the second interposer. It should be noted that terms such as xe2x80x9ctopxe2x80x9d, xe2x80x9cbottomxe2x80x9d, xe2x80x9cverticalxe2x80x9d, xe2x80x9chorizontalxe2x80x9d, xe2x80x9cfrontxe2x80x9d, xe2x80x9cbackxe2x80x9d, xe2x80x9crearxe2x80x9d, xe2x80x9coverxe2x80x9d, xe2x80x9cunderxe2x80x9d, xe2x80x9cbelowxe2x80x9d and the like as used in this present disclosure should be understood as referring to an arbitrary frame of reference, rather than to the ordinary gravitational frame of reference. Thus, the upward vertical direction of a component or assembly may extend upwardly, downwardly or horizontally in the normal gravitational frame of reference. In preferred embodiments the second surface also faces toward the top surface.
The conductive structures of this aspect of the flexible chip carrier are exposed at the first surface of the first interposer. In certain preferred embodiments, the conductive structures include parts (1) that positions within the first interposer but are accessible via the first surface of the first interposer or (2) that are partially embedded in the first interposer and are extended above the first surface of the first interposer. In other preferred embodiments, such parts are disposed on the first surface of the first interposer. The conductive structures also preferably extend through both the first and second interposers.
The planar leads of this aspect of the flexible chip carrier are exposed at the bottom surface of the second interposer. In certain preferred embodiments, the planar leads are positioned within the first interposer but are electrically accessible via the first surface of the first interposer. In other preferred embodiments, the planar leads are partially embedded in the first interposer and are extended below the bottom surface of the second interposer. In yet other preferred embodiments, the planar leads are disposed on the bottom surface of the second interposer. Each planar lead is electrically connected to at least one of the conductive structures. Each planar lead may include a terminal end that is electrically connected to one of the conductive structures and a tip end that is offset from such terminal end. In alternative embodiments, additional interposers may also be disposed between the first and second interposers of this aspect of the present invention so that the electrically conductive paths between the conductive structures and the planar leads may be routed or redistributed as desired.
In preferred embodiments, the flexible chip carrier may further include joining units such as solder balls. Each of the joining units is electrically connected to one of the tip ends.
Another aspect of the present invention provides a connection component that is similar to the above-described flexible chip carrier except the planar leads are not present and the joining units are directly connected to the conductive structures. Additional interposers may also be disposed between the first and second interposers of this aspect of the present invention so that the electrically conductive paths between the conductive structures and the joining units may be routed or redistributed as desired.
Another aspect of the present invention provides a microelectronic component comprising a connection component of the present invention and a microelectronic element having a front surface and a plurality of contacts exposed at the front surface. The microelectronic element is disposed over the connection component, and each of the contacts is electrically connected to one of the conductive structures. The microelectronic element may be, for example, a semiconductor chip, a packaged semiconductor chip, a semiconductor wafer or a multi-chip module.
In one preferred embodiment of the microelectronic component of the present invention, the front surface of a first microelectronic element faces the first surface of the first interposer, and contacts exposed on such front surface are flip chip bonded to the conductive structures. Further processing of this microelectronic component may yield a microelectronic component having one or more microelectronic elements. For example, a second microelectronic element having second contacts may be attached to the rear or back side of the first microelectronic element and such second contacts, which face away from the first microelectronic element, may be electrically connected to additional conductive structures by wirebonds to form a microelectronic component having stacked microelectronic elements.
In another preferred embodiment of the microelectronic component of the present invention, the contacts are wire bonded to the conductive structures. In preferred embodiments, the first surface of the first interposer includes a central region and a peripheral region surrounding the central region. The microelectronic element is disposed over the central region such that the front surface of the microelectronic element faces away from the first surface of the first interposer. Wirebonds are used to electrically connect the contacts to the conductive structures. The microelectronic component of this embodiment may also include one or more additional microelectronic elements that are stacked or otherwise connected to the first microelectronic element.
In preferred embodiments of the microelectronic component of the present invention, the CTE of the first interposer and the CTE of the microelectronic element are substantially similar.
Another aspect of the present invention provides an electronic device comprising the microelectronic component of the present invention and a support substrate having a plurality of electrically conductive contact pads. In preferred embodiments, the support substrate is a printed circuit board having contact pads that are disposed in a pattern corresponding to the pattern of the joining units. The microelectronic component is positioned such that the bottom surface of the second interposer faces the printed circuit board, and each joining unit of the microelectronic component is electrically connected to one of contact pads of the support substrate. Preferably, at least one of the joining units is disposed or positioned below the microelectronic element of the microelectronic component.
Another aspect of the present invention provides a method of making a microelectronic component. Such method has the following steps that may be performed preferably, but not necessarily, in the order presented below to make the microelectronic component. A first interposer having first and second surfaces that are oppositely facing and a second interposer having top and bottom surfaces that are oppositely facing are provided. This second interposer is more flexible than the first interposer. The top surface of the second interposer is positioned or disposed below the second surface of the first interposer. In preferred embodiments, the top surface of the second interposer faces the second surface of the first interposer. A layer of a metal is provided on the bottom surface of the second interposer and is circuitized so that a plurality of planar leads are formed. In preferred embodiments, each planar lead has a tip end and a terminal end. A plurality of openings are formed. These openings extend through both the first and second interposers and expose the terminal ends of the planar leads. An electrically conductive material is disposed in such openings. A microelectronic element such as a semiconductor chip having a front surface and a plurality of contacts exposed at its front surface is disposed over the first surface of the first interposer, and each contact is electrically connected to one of the terminal ends by the electrically conductive material.
Another aspect of the present invention provides another method of making a microelectronic component. In this method, a microelectronic element is disposed over the first surface of the first interposer of one of the connection components of the present invention such that the front surface of the microelectronic element faces away from the first surface. Each of the contacts exposed at the front surface of the microelectronic element is electrically connected to one of the conductive structures exposed at the first surface. In preferred embodiments, the contacts are electrically connected to the conductive structures by wirebonds.
The objects, features and advantages of the present invention will be more readily apparent from the detailed description of the preferred embodiments set forth below, taken in conjunction with the accompanying drawings.